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STRUCTURE PRODUCT SERIES
Silicon Monolithic Integrated Circuit Low ESR Capacitor, 1A Low Dropout Voltage Regulator Output Current : 1A High Output Voltage Precision : 1 High Input Voltage : 35V
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TYPE FEATURES
ABSOLUTE MAXIMUM RATINGSTa=25
Parameter Symbol Limits Unit Supply Voltage 1 Vcc -0.3+35.0 V Power Dissipation 2 Pd 1.2 W Operating Temperature Range Topr -40+105 Storage Temperature Range Tstg -55+150 Maximum Junction Temperature Tjmax 150 1 Not to exceed Pd. 2 Reduced by 9.6mW / C over Ta = 25C, when mounted on glass epoxy board: 70mmx70mmx1.6mm.
OPERATING CONDITIONSTa=25
Parameter Supply Voltage Output Current Symbol Vcc Io Min. 10.0 0 Max. 25.0 1.0 Unit A
NOTE : This product is not designed for protection against radioactive rays.
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ELECTRICAL CHARACTERISTICS Unless otherwise specified, Ta=25, Vcc=14V, Io=0mA
Parameter Bias Current Output Voltage Dropout Voltage Ripple Rejection Line Regulation Load Regulation Temperature Coefficient of Output Voltage 1 ein : Input Voltage Ripple Symbol Ib Vo Vd R.R. Reg.I Reg.L Tcvo.1 Tcvo.2 Limit Min. 8.91 40 Typ. 0.6 9.00 0.3 50 20 Vox0.010 +0.04 0.005 Max. 1.0 9.09 0.5 60 Vox0.015 Unit mA V V dB mV V / / Io=500mA Vcc=Vox0.95, Io=500mA 1 f=120Hz,ein =1Vrms, Io=100mA Vcc=1025V Io=5mA1A Io=5mA,Tj=-40-20 Io=5mA,Tj=-20+105 Conditions
PHYSICAL DIMENSIONS, MARKING
Marking
Lot.No.
TO252S-3 UNIT : mm
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BLOCK DIAGRAM
GND
FIN
Pin Number , Pin Name
Pin Number
VREF Bandgap Reference OCP Over Current Protection Circuit TSDThermal Shut Down Circuit Driver Power Transistor Driver
Pin Name
Function Power Supply Pin N.C. Pin Output Pin
1 2 3
Vcc N.C. Vo GND
VREF
Driver
OCP TSD
FIN
GND
1
2
3
Vcc
N.C.
Vo
Operation Notes
1. Absolute maximum ratings Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode) when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. 2. Electrical characteristics described in these specifications may vary, depending on temperature, supply voltage, external circuits and other conditions. Therefore, be sure to check all relevant factors, including transient characteristics. 3.GND potential The potential of the GND pin must be the minimum potential in the system in all operating conditions. Ensure that no pins are at a voltage below the GND at any time, regardless of transient characteristics. 4.Ground wiring pattern When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. The power supply and ground lines must be as short and thick as possible to reduce line impedance. 5.Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply or GND pins (caused by poor soldering or foreign objects) may result in damage to the IC. 6.Operation in strong electromagnetic fields Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in applications where strong electromagnetic fields may be present. 7.Testing on application boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC's power supply should always be turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8.Thermal consideration Use a thermal design that allows for a sufficient margin in light of the Pd in actual operating conditions. Consider Pc that does not exceed Pd in actual operating conditions. PdPc Tjmax : Maximum junction temperature=150, Ta : Peripheral temperature[] , ja : Thermal resistance of package-ambience[/W], Pd : Package Power dissipation [W], Pc : Power dissipation [W], Vcc : Input Voltage, Vo : Output Voltage, Io : Load, Ib : Bias Current Package Power dissipation : Pd (W)(TjmaxTa)ja Power dissipation : Pc (W)(VccVo)xIoVccxIb 9.Vcc pin Insert a capacitorcapacitor1F between the Vcc and GND pins. The appropriate capacitance value varies by application. Be sure to allow a sufficient margin for input voltage levels.
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10.Output pins It is necessary to place capacitors between each output pin and GND to prevent oscillation on the output. Usable capacitance values range from 1F to 1000F. Ceramic capacitors can be used as long as their ESR value is low enough to prevent oscillation (0.001 to 20). Abrupt fluctuations in input voltage and load conditions may affect the output voltage. Output capacitance values should be determined only through sufficient testing of the actual application. 11.Over current protection circuit (OCP) The IC incorporates an integrated over-current protection circuit that operates in accordance with the rated output capacity. This circuit serves to protect the IC from damage when the load becomes shorted. It is also designed to limit output current (without latching) in the event of a large and instantaneous current flow from a large capacitor or other component. These protection circuits are effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous or transitive operation of the protection circuits. 12.Thermal shutdown circuit (TSD) The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used after this function has activated, or in applications where the operation of this circuit is assumed. 13.Applications or inspection processes where the potential of the Vcc pin or other pins may be reversed from their normal state may cause damage to the IC's internal circuitry or elements. Use an output pin capacitance of 1000F or lower in case Vcc is shorted with the GND pin while the external capacitor is charged. Insert a diode in series with Vcc to prevent reverse current flow, or insert bypass diodes between Vcc and each pin. 14.Positive voltage surges on VCC pin A power zener diode should be inserted between VCC and GND for protection against voltage surges of more than 35V on the VCC pin. 15.Negative voltage surges on VCC pin A schottky barrier diode should be inserted between VCC and GND for protection against voltages lower than GND on the VCC pin. 16. Output protection diode Loads with large inductance components may cause reverse current flow during startup or shutdown. diode should be inserted on the output to protect the IC.
In such cases, a protection
17.Regarding input pins of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Resistor (Pin A) (Pin B)
Transistor (NPN) B E C
(Pin B) B C E GND N Parasitic elements or transistors
N P+ N P N P P+ N Parasitic elements GND N P+ N
P
P+
P substrate Parasitic elements or transistors GND (Pin A) Parasitic elements
Example of Simple Monolithic IC Architecture
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Notice
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Notes
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